1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more particularly, to dynamic random access memory (DRAM) devices in which the number of memory banks to be refreshed may be changed.
2. Description of the Related Art
Dynamic random access memories (DRAMs) periodically refresh memory cells therein. As memory capacity increases, it generally takes longer to refresh memory cells, and memory banks may not be able to perform other operations while refreshing the memory cells.
In addition, when refreshing all the memory banks at once, a semiconductor memory device may not be able to perform other operations, and refreshing all the memory banks at once may slow down the overall speed of the semiconductor memory device.
Therefore, if a semiconductor memory device includes a plurality of memory banks, it generally refreshes the memory banks one by one. In this case, a memory bank to be refreshed is designated. To this end, an external memory controller generates a bank address indicating the memory bank to be refreshed. The bank address is input to a bank address input terminal of the semiconductor memory device to control the refreshing of the memory bank.
FIG. 1 is a block diagram of a conventional semiconductor memory system performing a refresh operation. Referring to FIG. 1, the semiconductor memory system includes a memory controller 101 and a plurality of DRAMs 103. The memory controller 101 outputs a refresh command signal and an address of a memory bank to be refreshed to the DRAMs 103 such that the DRAMs 103 can refresh the memory bank. Each of the DRAMs 103 includes a plurality of memory banks 111, 113, 115, and 117, a bank address buffer 121, a command buffer 123, a command decoder 125, a delay circuit 127 for guaranteeing a refresh cycle, and a refresh control block 129.
Each of the memory banks 111, 113, 115, and 117 includes a plurality of memory cells to store data and needs to be refreshed to prevent discharging of the data. In the conventional semiconductor memory system, only one memory bank selected by the refresh control block 129 is refreshed while the other memory banks perform other operations. The command buffer 123 receives the refresh command signal from the memory controller 101 and stores the refresh command signal. The command decoder 123 decodes and interprets the refresh command signal.
The delay circuit 127 receives a refresh-start signal from the command decoder 125 and outputs a refresh-stop signal to the control block 129 after a period of time sufficient for the memory bank to be refreshed completely. The refresh control block 129 enables a wordline (W/L) of the memory bank and refreshes the memory bank in response to a bank address output from the bank address buffer 121 and the refresh-start command signal output from the command decoder 125. The refresh control block 129 finishes refreshing the memory bank in response to the refresh-stop signal output from the delay circuit 127.
The number of bank address pins through which bank addresses are input to the DRAMs 103 is fixed. If one of the DRAMs 103 includes four memory banks as illustrated in FIG. 1, there are two bank address pins. Thus, one of the four memory banks can be designated in response to a bank address signal.
Such a method of designating a memory bank to be refreshed using a bank address cannot be used to refresh a plurality of memory banks because only one memory bank is selected. Moreover, because only one memory bank is selected and refreshed, it may take a long time to refresh all the memory banks included in the DRAMs 103. Further, as memory capacity increases, refreshing may take even a longer time. Therefore, it may be difficult to increase the time allotted for other operations of the semiconductor memory system, such as, for example, reading and writing operations.